1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus including a data compression test circuit.
2. Related Art
A semiconductor memory apparatus has a large number of memory cells and can store high capacity data. In order to improve the reliability of the semiconductor memory apparatus, a test is generally performed to confirm whether a fail occurs in a memory cell, and a repair is conducted to replace a memory cell having the fail with a separately provided memory cell. However, since the semiconductor memory apparatus has a large number of memory cells as mentioned above, it is impossible to test the memory cells one by one to confirm whether a fail has occurred. Therefore, a test method capable of confirming a normal operation of the memory cells of the semiconductor memory apparatus within a short period of time is needed.
FIG. 1 is a diagram schematically illustrating the configuration of a conventional semiconductor memory apparatus. Referring to FIG. 1, the semiconductor memory apparatus compresses data outputted through data input/output lines from memory banks BANK0 through BANK3, and tests if a fail occurs in a memory cell by simultaneously determining compressed data. This is referred to as a data compression test for the semiconductor memory apparatus. In detail, in the case where first, third and fifth data are stored as high level data in a first memory bank BANK0, a test circuit compresses the first, third and fifth data into one data. At this time, if all of the three data have a high level, is a determination signal having, for example, a high level, is outputted and it can be appreciated that the data are normally outputted. If any one of the three data has a different level, a determination signal having, for example, a low level, is outputted and it can be appreciated that the data are not normally outputted.
FIG. 1 shows that a test is performed by compressing the data of the first bank BANK0. In FIG. 1, a 16-bit data stored in the first memory bank BANK0 of a lower memory region LDQ are compressed by a data compression unit 11 of a test circuit 10 and are loaded on global lines GIO_00<0>through GIO_03<0>. A determination unit 12 of the test circuit 10 determines whether all of the data loaded on the global lines GIO_00<0>through GIO_03<0>have the same level. Similarly, a 16-bit data stored in the first memory bank BANK0 of an upper memory region UDQ are compressed by a data compression unit 21 of a test circuit 20 and are loaded on global lines GIO_04<0>through GIO_07<0>. A determination unit 22 of the test circuit 20 determines whether all of the data loaded on the global lines GIO_04<0>through GIO_07<0>have the same level.
Therefore, the number of global lines for compressing and testing the data of the first memory bank BANK0 of the lower memory region LDQ becomes 4, and the number of global lines for compressing and testing the data of the first memory bank BANK0 of the upper memory region UDQ becomes 4 as well. As a result, the total number of is global lines necessary for one memory bank becomes 8. Therefore, in order to test a semiconductor memory apparatus which has 8 memory banks, total 64 global lines are needed.
Meanwhile, in order to elevate the degree of integration of a semiconductor apparatus, a three-dimensional semiconductor apparatus has been developed, in which a plurality of chips are stacked and packaged as a single package. Due to the fact that two or more chips are vertically stacked, the three-dimensional semiconductor apparatus can achieve an increased degree of integration in substantially the same space.
Also, recently, a through-silicon via (TSV) type semiconductor apparatus has been disclosed in the art, in which silicon vias are formed through a plurality of stacked chips so that all of the chips are electrically connected to one another. The TSV type semiconductor apparatus in which the chips are electrically connected by means of the silicon vias which vertically pass through the chips efficiently decreases the area of a package for the TSV type semiconductor apparatus when compared to a semiconductor apparatus in which respective chips are electrically connected through bonding wires bonded adjacent to the edges of the chips.
In the three-dimensional semiconductor apparatus, the number of global lines necessary to compress and test data in the same way as the conventional art dramatically increases. For example, in the case of manufacturing a single semiconductor apparatus by stacking 8 chips, if the same manufacturing process is used as in the conventional art, 64*8, that is, total 512 global lines are needed. In particular, in order to perform a test after a semiconductor memory apparatus is packaged, TSVs having a number corresponding to the number of the global lines are needed. Hence, a chip size and a layout area increases, which leads to an increase in the manufacturing cost.